Opella-XD for ARC

Ultra-high-speed JTAG Debug Probe

Ashling's OPELLA-XD is a powerful JTAG debug probe for embedded development with ARC International's ARC™ configurable RISC cores.  Developed in cooperation with ARC International plc, the Opella-XD probe integrates with ARC's MetaWare or GNU GDB Debuggers under Windows™ or Linux based hosts.

Advanced features of Opella-XD include:

• Fast, easy-to-install USB 2.0 High-Speed Interface (480Mb/s)
• Supports all popular hardware debug protocols
• Unique Auto-conditioning Probe provides maximum possible download speed to target with fastest JTAG clock frequencies
• Hot-plug support allows post-mortem debugging
• Fast, trouble-free Plug-and-Play installation
• Supplied with 20-pin .1” Target Probe Assembly for Debug interface to target device or target FPGA.
• Optional 15-pin D-Type JTAG adapter for Debug interface to target device or ARCangel board.
• Opella-XD supports FPGA Programming on ARC FPGA targets (e.g. ARCangel) or user’s target board
• Wide target voltage range:  0.9V to 3.6V
• Versatile Target-Reset and Test-Port-Reset support
• Built-in diagnostics instantly show status of Target, Debug Probe and USB link

Benefits of Opella-XD to the embedded hardware developer:

• Accelerates the entire embedded-hardware debug process: ultra-fast installation, code download and flash programming saves time at every code rebuild

• Instantly auto-configures to target system

• Long-term investment: works with all popular target architectures and compilers

• Helps with the most difficult debugging tasks: hardware bring-up, operating-system booting, post-mortem debugging

• Future-proof: works with latest hardware-debug protocols, all popular host operating-systems

• Compact, easy-to-install target probe cables support all popular debug interfaces

• High-speed USB2.0 (480Mb/s) interface to host PC
• Target JTAG clock rates up to 100MHz
• Auto-conditioning for fast JTAG clock frequencies
• Configurable Target-Reset and Test-Port-Reset, under full user control
• Fine-grained adjustment of JTAG clock frequency from 1KHz to 100MHz
• Supports target operating voltages from 0.9V to 3.6V. Opella-XD detects and automatically configures for the appropriate target voltage.
• “Hot-plug” support; allows connection to a running target without resetting or halting
• Fully powered by USB interface; no external power-supply needed
• Display/read/write of target system memory and peripheral registers
• Support for all on-chip hardware breakpoints; unlimited software breakpoints
• Target Reset control and Remote Reset detect
• Run/stop control of target application including go, halt, step over, step into and step out of
• Operates with ARC’s MetaWare or GNU  GDB Debuggers under Windows™ or Linux based hosts
• Support for Multi-core debug
• Support for multiple Opella connected to the same PC (this supports Multi-core systems where each core has a unique JTAG interface)
• ARCangel™ Development Board System FPGA programming support; allows easy configuration using an Opella connection between your host PC and ARCangel™
• All ARCtangent-A4, ARCtangent-A5, ARC 600, ARC 700, Energy Pro EP20 and EP30 cores are supported

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ARCtangent and ARCangel are trademarks or registered trademarks of ARC International plc