05/11/2022 » Intel® partners with Ashling to provide Ashling’s RiscFree™ Toolchain for Intel FPGAs

Intel Extends its Multi-Platform RISC-V Support by Partnering with Ashling

White Paper | Intel® FPGAs – Soft Embedded Processors

Executive Summary. Intel has partnered with Ashling, a prominent RISC-V solutions provider, to expand multi-platform RISC-V support. By migrating soft processors in Intel® FPGAs to the open RISC-V standard and integrating Ashling’s RiscFree™ IDE and Unified Debugger, Intel provides customers with a powerful ecosystem of modern compilers, debuggers, and operating systems.

Intel’s RISC-V Strategy

Intel has a long legacy of pioneering processor design, from the Intel 4004 (1971) to the globally dominant x86 ISA (1978). In February 2022, Intel joined RISC-V International as part of its strategy to expand open hardware ecosystems. Intel partners with Ashling, Andes Technology, Esperanto, SiFive, and Ventana Micro Systems to strengthen the RISC-V ecosystem.

Value of RISC-V for FPGA Customers

RISC-V offers modularity, extensibility, and performance benefits without legacy constraints. Its rapid adoption is driving innovation across embedded automotive, HPC, AI, and 5G. For FPGA users, RISC-V soft-cores provide flexible upgrades, broad tool support, and a standard debug environment.

Intel Nios® V Processors

Intel introduced the Nios® V soft-core processor family, based on RISC-V, as the successor to Nios® II. Variants include the Nios V/m (microcontroller class), future general-purpose, application-class, and Linux-capable 64-bit versions. These processors enable easy migration from Nios II while offering higher performance and broader OS/RTOS support (Zephyr, FreeRTOS, Linux).

Value of RiscFree for Intel FPGA & ASIC Customers

Ashling’s RiscFree™ IDE and Unified Debugger provide a fully open-source, Eclipse-based environment supporting both homogeneous and heterogeneous multi-core debug. Key features include:

    • Integrated GCC compiler toolchain with newlib/picolibc libraries

    • Runtime debug with register view for Nios V and Arm cores

    • Real-time trace (on-chip and off-chip)

    • OS/RTOS awareness (Zephyr, FreeRTOS, µC/OS-II, Linux kernel debug)

    • Custom instruction & extension support

    • Single probe debug for mixed Arm + RISC-V environments

Intel eASIC™ Device: A Path from FPGA to ASIC

Intel provides migration paths from FPGAs to structured ASICs (Intel® eASIC™) and standard-cell ASICs, reducing cost and power while increasing performance. This enables FPGA designs with Nios V processors to be hardened into efficient ASICs.

Why Ashling?

Ashling brings 30+ years of embedded tools expertise and leadership in RISC-V debug and trace standards. Its partnership with Intel ensures co-engineering integration with Quartus® and FPGA toolchains, delivering tightly coupled workflows for project build, debug, and trace.

Summary

Intel’s adoption of RISC-V and partnership with Ashling extends multi-platform support, enabling development on Intel FPGAs with Nios V processors and deployment to Intel eASIC and ASIC platforms. This combination delivers flexibility, performance, and open-source toolchains unmatched by proprietary ecosystems.

Additional resources: Intel Agilex FPGA | Intel Nios V Processors | Ashling RiscFree SDK

Authors: Shreya Mehrotra & Findlay Shearer (Intel), Hugh O’Keeffe & Nadim Shehayed (Ashling).

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