December 6, 2021
San Francisco, CA USA (RISC-V Summit 2021). Ashling announced today that Ashling’s RiscFree™ Toolchain will be extended to support the broad range of Alibaba RISC-V CPU IPs including the open source XuanTie E902, E906, C906, and C910.
RiscFree™ is Ashling’s Integrated Development Environment (IDE), Compiler, and Debugger for RISC-V development and now adds support for Alibaba RISC-V CPUs including both the 32-bit and 64-bit cores.
“We’re happy to add support for Alibaba as one of the leading RISC-V core vendors. Ashling’s RiscFree™ with its Different Cores, One Solution feature set now brings the power of heterogeneous, multi-core debugging to Alibaba’s RISC-V CPU users, allowing a single instance of RiscFree™ to debug any number of heterogeneous and homogeneous cores.” – Hugh O’Keeffe, Managing Director of Ashling
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The Xuantie series processors are RISC-V-based open source CPUs from Alibaba T-Head, designed for a wide range of embedded and compute applications.
For more information on Ashling’s RiscFree™ see: Ashling RiscFree SDK.
Ashling have been a leading provider of Embedded Development Tools & Services since 1982 with design centres in Limerick, Ireland and Chennai, India and sales and support offices in Europe, Asia Pacific, the Middle East and America. With over thirty years’ experience, Ashling develops tools for embedded systems engineers including high-speed Debug and Trace Probes, IDEs, Debuggers, Compilers, and Simulators. Ashling supports all major embedded architectures including ARC, Arm, MIPS, Power Architecture, and RISC-V through its RiscFree™ platform. Visit www.ashling.com for more details or contact Nadim Shehayed: nadim@ashling.com.
The RISC-V open architecture ISA is under the governance of RISC-V International.
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