December 9th, 2019 – San Jose, CA (RISC-V Summit). Ashling, a leading provider of embedded development tools, announced full support in Ashling’s RiscFree™ IDE and Debugger for multi-core heterogeneous software development all from within a single environment using a single debug probe.
The RiscFree™ IDE and Debugger allows full specification of SoC core configurations and supports cores from RISC-V, Synopsys ARC, Arm, and (coming soon) Wave Computing MIPS. Debug interfaces supported include JTAG, cJTAG, and Arm SWD Coresight.
Combined with Ashling’s Opella-XD JTAG or Ultra-XD Trace probes, RiscFree™ provides dedicated debug views for each SoC core, easily switched between to view or control individual cores.
“We’re happy to introduce our latest debugging technology at the RISC-V Summit 2019 developed in close co-operation with our RISC-V customers and ecosystem partners. As RISC-V uptake continues to build, we believe the time is now right to address the emerging tools requirements for SoC designs containing RISC-V and other cores. This new technology will put Ashling in a unique position as the leading debug-focused toolchain in the embedded development market.” – Hugh O’Keeffe, VP of Global Engineering, Ashling.
For more information, visit: Ashling RiscFree | Ashling Multi-Core Debug | RISC-V International
The RISC-V open architecture ISA is under the governance of RISC-V International.
Ashling is a world-class technology partner offering integrated solutions, tools, and design services at the heart of the embedded environment. Its solutions are used across automotive, aerospace, healthcare, and IoT. Ashling’s HQ and Engineering Centre is in Limerick, Ireland, with worldwide sales and support representatives. Visit www.ashling.com for more details.
Nadim Shehayed, Business Development – nadim.shehayed@ashling.com
Hugh O’Keeffe, Managing Director – hugh.okeeffe@ashling.com
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