03/10/2026 » Ashling and Siemens accelerate Siemens’ Tessent Embedded Analytics bring up, debug, and in field insight for complex SoCs

 

 

Embedded World 2026, Nuremberg, Germany | March 10th, 2026.

Ashling announced a joint cooperation with Siemens to deliver a tightly integrated hardware and software solution for teams deploying Siemens’ Tessent™ Embedded Analytics software in advanced system on chip (SoC) designs. The cooperation brings together Siemens’ Tessent Embedded Analytics Host Suite and Ashling’s RiscFree™ SDK plus the Opella-XD and Vitra-XS debug and trace probes.

 

Figure 1. Ashling’s RiscFree integration into Siemens’ Tessent Embedded Analytics Host Suite

 

As SoCs grow in complexity, engineering teams need faster paths from first power on to reliable system wide visibility, both in the lab and in the field. By aligning Host Suite capabilities with Ashling’s proven debug and trace platform, Siemens and Ashling aim to simplify integration, improve developer productivity, and accelerate time to insight across the SoC lifecycle.

 

The cooperation focuses on seamless connectivity and workflow integration. Ashling Opella-XD and Vitra-XS probes provide the JTAG connection, and where supported, enable access to trace and analytics data between the host computer and the SoC. Both probes support UltraSight-V for RISC-V based debug and trace and the Host SDK Communicator interface, providing tight integration into Siemens’ Tessent Embedded Analytics Host Suite.

 

Alongside probe integration, Ashling’s RiscFree SDK provides an integrated development and debug environment designed as a more capable alternative to a Visual Studio Code/GDB/OpenOCD setup. With RiscFree, developers can move from basic bring up to advanced multicore, heterogeneous debug and trace analysis in a single environment, while also aligning with Host Suite based automation, monitoring, and analytics workflows.

 

Figure 2. Ashling’s RiscFree Debugging Suppor

 

“Customers want a smooth, dependable path from silicon bring up to real product insight, without stitching together fragile toolchains,said Hugh O’Keeffe, CEO at Ashling. “This cooperation ensures Ashling probes and RiscFree fit cleanly into the Siemens Host Suite workflow, giving engineering teams a practical and scalable way to debug, trace, and extract value from Tessent Embedded Analytics enabled SoCs.”

 

“As Tessent Embedded Analytics expands visibility from the lab into deployed systems, Tessent Host Suite plays a key role in enabling interactive debug and automation at scale,” said Ankur Gupta, executive vice president for IC portfolio, Siemens EDA, Siemens Digital Industries Software. “Working with Ashling strengthens the ecosystem with proven probe hardware and an integrated software experience, helping customers reduce integration effort and speed up adoption.”

 

The joint solution is intended for semiconductor and system companies building RISC-V and other advanced SoC platforms that require high quality debug, trace, and post deployment analytics to support faster development cycles and more reliable products.

 

About Ashling
Ashling is a leading provider of development of tools and solutions for embedded systems and the semiconductor industry. With a focus on enabling software design for next-generation processors and SoCs, Ashling offers cutting-edge debugging tools, trace probes, and development environments. Learn more at https://www.ashling.com/ and go direct to https://ashling.com/products/ for details on the Ashling product range.

 

Note: A list of relevant Siemens trademarks can be found here.