March 28, 2022.
Silicon Valley, CA, USA . Ashling and MIPS announced today that Ashling’s RiscFree™ Toolchain has been extended to support MIPS RISC-V ISA based IP cores. RiscFree™ is Ashling’s Integrated Development Environment (IDE) including a compiler and debugger for RISC-V development, now enhanced with MIPS’ proven Core Framework Platform.
“We are delighted to have Ashling RiscFree™ support for our RISC-V ISA IP cores. Our engineering teams have worked closely together developing the toolchain in parallel with the core IP and believe this can result in rapid time-to-market for our end customers.” – Don Smith, Vice President of Engineering at MIPS.
The Ashling RiscFree™ toolchain includes support for both code development and debug on MIPS RISC-V IP cores and provides advanced features such as multi-core and multi-cluster support, Linux debug awareness, real-time trace support, and cache awareness. It also comes with Ashling hardware probes for debug and trace. A targeted and optimized GCC toolchain is included and fully integrated into the RiscFree™ IDE.
“We are excited to see MIPS, one of the first companies to bring a RISC based architecture to the market back in the 1980s, now expanding to offer RISC-V ISA compliant cores. We’ve a long history of working together and believe the support of our market-leading RiscFree™ Toolchain will help in the rapid market adoption of their MIPS RISC-V ISA cores.” – Hugh O’Keeffe, CEO of Ashling.
For more information on Ashling’s RiscFree™ see: Ashling RiscFree SDK and for more information on MIPS see: MIPS.
Ashling has been a leading provider of Embedded Development Tools & Services since 1982 with design centres in Limerick, Ireland and Cochin, India and sales and support offices in Europe, Asia Pacific, the Middle East, and America. With over thirty years of experience, Ashling develops tools for embedded systems engineers including high-speed Debug and Trace Probes, IDEs, Debuggers, Compilers, and Simulators. Ashling supports all major embedded architectures including ARC, Arm, MIPS, Power Architecture, and RISC-V through its RiscFree™ platform. Visit www.ashling.com for more details.
MIPS is a leading developer of scalable RISC processor IP for high-end automotive, computing, and communications applications. With an ecosystem built over 35 years and billions of MIPS-based chips shipped, MIPS is accelerating RISC-V innovation for heterogeneous processing. Its solutions are uniquely configurable, enabling semiconductor companies to meet performance and power requirements and differentiate their devices.
The RISC-V open architecture ISA is governed by RISC-V International.
Ashling: Nadim Shehayed – nadim.shehayed@ashling.com
MIPS and the MIPS logo are trademarks or registered trademarks of MIPS Inc. in the United States and other countries. Other company, product, and service names may be trademarks or service marks of others.