September 3rd, 2025, Mountain View, CA, USA. Ashling will be attending the Synopsys Processor IP Summit in Mountain View where we’ll be showcasing our latest embedded development tools & solutions, including support for the Synopsys ARC-V (RISC-V based) Processor IP. As a Synopsys partner for over fifteen years, we’re happy to announce that our development tools now support the Synopsys ARC-V family (including the RMX, RHX and the RPX processors) as well as continued support for the “classic” ARC devices (including the EM, EV, HS, NPX and VPX). Our tools include:
Vitra-XS Debug and Trace Probe:Designed for embedded development, this probe supports multiple target architectures, including RISC-V systems with N-Trace and E-Trace, Classic ARC, and Arm systems using CoreSight™ trace technologies (ETM, PTM, etc.). It integrates seamlessly with Ashling’s enhanced RiscFree™ debugger, now featuring new Profiling, Code-coverage, and Dynamic Function-flow Timeline views.(Vitra-XS Datasheet)Please do drop by to our booth and say hello if you are planning on visiting the Synopsys Processor IP Summit.
Ashling is a world leader in the development of tools and solutions for embedded systems and the semiconductor industry. With a focus on enabling software design for next-generation processors and SoCs, Ashling offers cutting-edge debugging tools, trace probes, and development environments.
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