09/24/2019 » Ashling’s RiscFree™ Toolchain now supports Western Digital’s SweRV RISC-V Cores

September 24th, 2019 – Redwood Shores, CA. Ashling, a leading provider of embedded development tools, announced full tools support for Western Digital’s RISC-V open-source SweRV cores on their RiscFree™ Toolchain.

 

Western Digital’s SweRV Core is a 32-bit, 2-way superscalar, 9-stage pipeline core offering compelling capabilities for embedded devices supporting data-intensive edge applications such as storage controllers and industrial IoT.

 

RiscFree™ is Ashling’s Eclipse-based Integrated Development Environment (IDE) for RISC-V, providing a complete, seamless environment for RISC-V software development. Its single-shot installer automatically configures all tools to work “out-of-the-box.” Features include:

 

    • Eclipse-based IDE with full source and project creation, editing, build, and debug support

    • RISC-V compiler toolchain with optional user-specific customizations

    • Project wizards, templates, and examples for RISC-V devices from multiple vendors

For more information, visit: Ashling RiscFree | Western Digital SweRV Blog | RISC-V International

 

About RISC-V

The RISC-V open architecture ISA is governed by RISC-V International.

 

About Ashling

Ashling is a world-class technology partner offering integrated solutions, tools, and design services for embedded systems. Ashling collaborates with leading semiconductor vendors and provides tools used in diverse applications from automotive and aerospace to healthcare and IoT. Its HQ and Engineering Centre is in Limerick, Ireland, with worldwide sales and support representatives. Visit www.ashling.com for more details.

 

Contacts

Nadim Shehayed, Business Development – nadim.shehayed@ashling.com
Hugh O’Keeffe, Managing Director – hugh.okeeffe@ashling.com

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