December 6, 2021
San Francisco, USA (RISC-V Summit 2021). Ashling and Andes Technology announced today that Ashling’s RiscFree™ Toolchain will be extended to support the broad range of Andes RISC-V CPU IPs including support for the AndeStar™ V5 Performance and CoDense™ ISA Extension, leveraging the production-proven Andes GNU compiler.
RiscFree™ is Ashling’s Integrated Development Environment (IDE), Compiler, and Debugger for RISC-V development. It now supports Andes RISC-V CPUs including the 32-bit: N22, N25F, D25F, A25, A25MP, A27, A27L2, N45, D45, A45 & A45MP and the 64-bit: NX25F, AX25, AX25MP, NX27V, AX27, AX27L2, NX45, AX45 & AX45MP.
“Ashling’s RiscFree™ with its Different Cores, One Solution feature set now brings the power of heterogeneous, multi-core debugging to Andes RISC-V CPU users, allowing a single instance of RiscFree™ to debug any number of heterogeneous and homogeneous cores.” – Hugh O’Keeffe, Managing Director of Ashling.
“We are delighted to have Ashling RiscFree™ support Andes RISC-V CPU cores and offer an additional choice for our customers, particularly those working on heterogeneous SoC designs utilizing AndesCore™ V5 RISC-V processors with increased performance and reduced code size.” – Dr. Charlie Su, President and CTO of Andes Technology.
For more information on Ashling’s RiscFree™ see: Ashling RiscFree SDK and for details on Andes RISC-V CPU cores see: Andes RISC-V CPUs.
Ashling have been a leading provider of Embedded Development Tools & Services since 1982 with design centres in Limerick, Ireland and Chennai, India and sales and support offices worldwide. With over 30 years’ experience, Ashling develops tools for embedded systems engineers including high-speed Debug and Trace Probes, IDEs, Debuggers, Compilers, and Simulators. Ashling supports ARC, Arm, MIPS, Power Architecture, and RISC-V through its RiscFree™ platform. Visit www.ashling.com for more details.
Contact: Nadim Shehayed – nadim@ashling.com
Andes Technology, founded 16 years ago and a Founding Premier member of RISC-V International, is a leading supplier of high-performance, low-power 32/64-bit embedded processor IP solutions. Its fifth-generation AndeStar™ architecture is based on RISC-V. Andes’ V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit cores with DSP, FPU, Vector, Linux, superscalar, and multicore capabilities. Annual shipments of Andes-Embedded SoCs have exceeded 2 billion since 2020, with cumulative shipments surpassing 7 billion.
Contact: Hsiao-Ling Lin – hllin@andestech.com.
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