Ashling extends support to the Synopsys ARC‑V family (RISC‑V-based ISA) across SDK and probes.
Includes ARC‑V support within RiscFree (IDE, debugger, compiler, trace analytics) alongside ARC, Arm, RISC-V.
Enables heterogeneous debug for ARC‑V plus other cores.
Vitra‑XS: real-time trace for ARC‑V (RISC-V E‑Trace & N‑Trace) and ARC, plus heterogeneous support with Arm.
Opella‑XD: supports ARC‑V debug within Ashling ecosystem.
Recent support for Synopsys ARC‑V processors showcased at industry events (e.g., Processor IP Summit).